While monolithic integration of circuits continues to evolve, integration of separate integrated circuit (IC) chips provides advantageous product flexibility. Many techniques are employed to integrate a first IC chip, such as a memory chip, with a second IC chip, such as a logic or processor chip, with the general goals typically including lower cost and higher component density. One technique is “stacked-die” packages where one chip is stacked on another, and the two die are then packaged together on a substrate. Another technique is “package on package” (PoP) where two ball grid array (BGA) packages are installed atop each other with an interface to route signals between them.
While conventional PoP offers the advantage of functionally decoupling the packaged chips from one another, PoP imposes a z-height limitation the bottom package (PoPb). This limitation can be seen in FIG. 1 illustrating a conventional PoP assembly 100 including a top package 101 stacked upon a bottom package 105. As shown, the BGA interconnects 115 limit the bottom package 105 to a maximum z-height of H1.
As there are a limited number of standardized solder ball dimensions, a packaged chip having a z-height (H2) that exceeds H1 provided by the largest available BGA interconnect cannot be utilized as the bottom package (chip) in the conventional PoP assembly process because interference between the top and bottom packages (chips) would hinder electrical interconnection by BGA interconnects 115. Even where the bottom package 105 includes a flip-chip architecture, the largest chips, such as microprocessor chips, may have a chip thickness that causes the z-height H2 to exceed H1. As such, advantageous package-level chip integrations are hindered by conventional PoP architectures.
PoP architectures and techniques which allow bottom packages to have a greater z-height and a greater resolution of z-height offer advantageous flexibility to accommodate bottom packages of any z-height.